In many analog-to-digital converter (ADC) applications such as wireless receiver handsets, the bandwidth of the analog signal of interest is narrow relative to practical ADC sample-rates. Delta-sigma (ΔΣ) modulator ADCs are used almost exclusively in such applications because they offer exceptional efficiency and relax the analog filtering required prior to digitization. Continuous-time ΔΣ modulator ADCs with clock rates above several hundred MHz have been shown to be particularly good in these respects. See, e.g., W. Yang et al, “A 100 mW 10 MHz-BW CT ΔΣ Modulator with 87 dB DR and 91 dBc MD”, IEEE International Solid-State Circuits Conference, pp. 498-499, February 2008; G. Mittergger et al., “A 20-mW 640-MHz CMOS Continuous-Time ΔΣ ADC With 20-MHz Signal Bandwidth, 80-dB Dynamic Range and 12-bit ENOB,” IEEE Journal of Solid-State Circuits, vol. 41, no. 12, pp. 2641-2649, December 2006; Park et al, “A 0.13 μm CMOS 78 dB SNDR 87 mW 20 MHz BW CT ΔΣ ADC with VCO-Based Integrator and Quantizer,” IEEE International Solid-State Circuits Conference, pp. 170-171, February 2009; V. Dhanasekaran et al., “A 20 mHz BW 68 dB DR CT ΔΣ ADC Based on a Multi-Bit Time-Domain Quantizer and Feedback Element,” IEEE International Solid-State Circuits Conference, pp. 174-175, February 2009. Continuous-time ΔΣ modulators with sample-rates in excess of several hundred megahertz have been shown to be particularly efficient in these types of applications because they allow much of the interference filtering to be done in the digital domain.
Typical conventional analog ΔΣ modulators present significant design challenges when implemented in highly-scaled CMOS IC technology optimized for digital circuitry. Such conventional ΔΣ modulators require analog comparators, high-accuracy analog integrators, high-linearity feedback digital to analog converters (DACs), and low-noise, low-impedance reference voltage sources. Continuous-time ΔΣ modulators with continuous-time feedback DACs additionally require low-jitter clock sources. These circuit logic units are increasingly difficult to design as CMOS technology is scaled below the 90 nm node because the scaling tends to worsen supply voltage limitations, device leakage, device nonlinearity, signal isolation, and 1/f noise.
An alternate type of ΔΣ modulator avoids the analog components and consists of a voltage-controlled ring oscillator (ring VCO) with its inverters sampled at the desired output sample-rate followed by digital circuitry. See, e.g., Hovin et al., “Delta-Sigma Modulators Using Frequency-Modulated Intermediate Values,” IEEE Journal of Solid-State Circuits, vol. 32, no. 1, pp. 13-22, January 1997; Kim et al, “A Time-Based Analog-to-Digital Converter Using a Multi-Phase Voltage-Controlled Oscillator,” IEEE International Symposium on Circuits and Systems, pp. 3934-3937, May 2006; Naiknaware et al, “Time-Referenced Single-Path Multi-Bit ΔΣ ADC using a VCO-Based Quantizer,” IEEE Transactions on Circuits and Systems—II: Analog and Digital Signal Processing, vol. 47, no. 7, pp. 596-602, July 2000; Iwata et al., “The Architecture of Delta Sigma Analog-to-Digital Converters Using a Voltage-Controlled Oscillator as a Multibit Quantizer,” IEEE Transactions on Circuits and Systems—II: Analog and Digital Signal Processing, vol. 46, no. 7, pp. 941-945, July 1999; Wismar et al., “A 0.2 V, 7.5 μW, 20 kHz ΣΔ modulator with 69 dB SNR in 90 nm CMOS,” European Solid-State Circuits Conference, pp. 206-209, September 2007; Opteynde, “A Maximally-Digital Radio Receiver Front-End,” IEEE International Solid-State Circuits Conference, pp. 450-451, February 2010.
Galton and Taylor U.S. Pat. No. 8,542,138 advanced the state of the art, and is incorporated by reference herein. See, also G. Taylor, I. Galton, “A Mostly-Digital Variable-Rate Continuous-Time Delta-Sigma Modulator ADC,” IEEE Journal of Solid-State Circuits, vol. 45, no. 12, pp. 2634-2646, December, 2010. The patent discloses pseudo-differential mostly digital ADCs with a dual VCO-based ΔΣ modulator signal path calibration units.